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WM2624 Low Power 8-bit Serial Input DAC with Internal Reference
Production Data, November 2000, Rev 1.0
FEATURES
* * * * * * * * 8-bit Voltage Output DAC Single Supply from 2.7V to 5.5V Very Low Supply Current: - 1.5 mA in Slow Mode - 2.3 mA in Fast Mode DNL 0.2 LSB, INL 0.5 LSB (max) Monotonic over Temperature DSP Compatible Serial Interface Programmable Settling Time of 1s or 3.5s Typical Reference Output Buffer can Supply up to 1mA
DESCRIPTION
The WM2624 is an 8-bit voltage output, resistor string digital-toanalogue converter. It can operate with supply voltages between 2.7V and 5.5V and can be powered down under software control. Power down reduces current consumption to 10nA. The device has been designed for glueless interface to industry standard microprocessors and DSPs. The WM2624 is programmed with a 16-bit serial word including 4 control bits and 8 data bits. Excellent performance is delivered with a maximum DNL of 0.2LSBs. Monotonicity is guaranteed over the operating temperature range. The settling time of the DAC is programmable to allow for optimisation of speed versus power dissipation. The output stage is buffered by a rail-to-rail amplifier with a gain of two, which features a Class AB output stage. The on-chip voltage reference is available to external circuitry through the REF pin. It is buffered and can supply up to 1mA. Alternatively, an external reference can be used. A high impedance reference input buffer is included on the chip to interface to external references, whose source impedance may be high. The WM2623 is available in an 8-pin SOIC package. Commercial (0 to 70C) and Industrial (-40 to 85C) temperature range variants are available.
APPLICATIONS
* * * * * Digital Servo Control Loops Industrial Process Control Battery Powered Instruments and Controls Machine and Motion Control Devices Digital Offset and Gain Adjustment
ORDERING INFORMATION
DEVICE WM2624CD WM2624ID TEMP. RANGE 0 to 70C -40 to 85C PACKAGE 8-pin SOIC 8-pin SOIC
BLOCK DIAGRAM
VDD (8) REFERENCE OUTPUT BUFFER WITH OUPUT ENABLE X1
TYPICAL PERFORMANCE
0.1
REF(6)
1.024V/2.048V SELECTABLE REFERENCE
VDD = 2.7V, VREF = 1.024V, Speed = Fast Mode 0.08
0.06
REFERENCE INPUT BUFFER X1 DAC OUTPUT BUFFER
DNL - Digital Non-Linearity (LSBs)
2-BIT REFERENCE SELECT LATCH
0.04
0.02
0
DIN (1) SCLK (2) CSB (3) 16-BIT SHIFT REGISTER AND CONTROL LOGIC data
8-BIT DAC LATCH
X2
(7) OUT
-0.02
-0.04
-0.06
FS (4) 2-BIT CONTROL LATCH POWERDOWN/ SPEED CONTROL
-0.08
POWER-ON RESET
WM2624
-0.1 0 32 64 96 128 DIGITAL CODE 160 192 224 256
(5) GND
WOLFSON MICROELECTRONICS LTD
Lutton Court, Bernard Terrace, Edinburgh, EH8 9NX, UK Tel: +44 (0) 131 667 9386 Fax: +44 (0) 131 667 5176 Email: sales@wolfson.co.uk http://www.wolfson.co.uk
Production Data Datasheets contain final specifications current on publication date. Supply of products conforms to Wolfson Microelectronics' Terms and conditions.
2000 Wolfson Microelectronics Ltd.
WM2624 PIN CONFIGURATION
DIN SCLK CSB FS 1 2 3 4 8 7 6 5 VDD OUT REF GND
Production Data
PIN DESCRIPTION
PIN NO 1 2 3 4 5 6 7 8 NAME DIN SCLK CSB FS GND REF OUT VDD TYPE Digital input Digital input Digital input Digital input Supply Analogue in/out Analogue output Supply Serial data input Serial clock input Chip select. This pin is active low. Frame synchronisation for serial input data Ground Voltage reference DAC analogue output Positive power supply DESCRIPTION
ABSOLUTE MAXIMUM RATINGS
Absolute Maximum Ratings are stress ratings only. Permanent damage to the device may be caused by continuously operating at or beyond these limits. Device functional operating limits and guaranteed performance specifications are given under Electrical Characteristics at the test conditions specified. ESD Sensitive Device. This device is manufactured on a CMOS process. It is therefore generically susceptible to damage from excessive static voltages. Proper ESD precautions must be taken during handling and storage of this device. CONDITION Supply voltage, VDD to GND Digital input voltage Reference input voltage Operating temperature range, TA Storage temperature Lead temperature 1.6mm (1/16 inch) from package body for 10 seconds WM2624CD WM2624ID -0.3V -0.3V 0C -40C -65C MIN MAX 7V VDD + 0.3V VDD + 0.3V 70C 85C 150C 260C
RECOMMENDED OPERATING CONDITIONS
PARAMETER Supply voltage High-level digital input voltage Low-level digital input voltage Reference voltage to REF pin Load resistance Load capacitance Serial clock frequency Operating free-air temperature SYMBOL VDD VIH VIL VREF RL CL fSCLK TA WM2624CD WM2624ID 0 -40 VDD = 2.7V to 5.5V VDD = 2.7V to 5.5V See Note GND 2 10 100 20 70 85 TEST CONDITIONS MIN 2.7 2 0.8 VDD - 1.5 TYP MAX 5.5 UNIT V V V V k pF MHz C C
Note: Reference input voltages greater than VDD/2 will cause clipping for large DAC codes. The reference output buffer must be disabled if an external reference is used.
WOLFSON MICROELECTRONICS LTD
PD Rev 1.0 November 2000
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Production Data
WM2624
ELECTRICAL CHARACTERISTICS
Test Conditions: RL = 10k, CL = 100pF. VDD = 5V 10%, VREF = 2.048V and VDD = 3V 10%, VREF = 1.024V over recommended operating freeair temperature range (unless noted otherwise). PARAMETER Static DAC Specifications Resolution Integral non-linearity Differential non-linearity Zero code error Gain error D.C. power supply rejection ratio Zero code error temperature coefficient Gain error temperature coefficient DAC Output Specifications Output voltage range Output load regulation Power Supplies Active supply current Power down supply current Dynamic DAC Specifications Slew rate SR DAC output 10% to 90% Slow Fast See Note 8 DAC output 10% to 90% Slow Fast See Note 9 DIN = 0 to 1, fCLK = 100kHz fs = 480KSPS, fOUT = 1kHz, Load = 10k / 100pF See Note 10 53 47 IDD 2k to 10k load See Note 7 No load, DAC value = 128, all digital inputs 0V or VDD Fast Slow 0 0.1 VDDi 0.25 V % FS INL DNL ZCE GE PSRR See Note 1 See Note 2 See Note 3 See Note 4 See Note 5 See Note 6 See Note 6 -65 10 10 8 0.3 0.07 0.5 0.2 10 0.6 bits LSB LSB mV % FSR dB ppm/C ppm/C SYMBOL TEST CONDITIONS MIN TYP MAX UNIT
2.3 1.5 10
3.3 1.9
mA mA nA
1.5 8 3.5 1 5 57 48 -50 50 62 -48 7 3
V/s V/s s s nV-s dB dB dB dB
Settling time
ts
Glitch energy Signal to noise ratio Signal to noise and distortion ratio Total harmonic distortion Spurious free dynamic range Reference Output (Internal Reference) Low reference voltage High reference voltage Output Source/Sink Current Load capacitance Reference Input (External Reference) Reference input resistance Reference input capacitance Reference feedthrough Reference input bandwidth RREFIN CREFIN VREFL VREFH IREF SNR SNRD THD SFDR
1.003 VDD > 4.75V 2.027
1.024 2.048
1.045 2.069 1 100
V V mA pF
10 5 VREF = 1VPP at 1kHz + 1.024V DC, DAC code 0 VREF = 0.2VPP + 1.024V DC DAC code 128 Slow Fast -80
M pF dB
0.525 1.3
MHz MHz
WOLFSON MICROELECTRONICS LTD
PD Rev 1.0 November 2000
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WM2624
Production Data
Test Conditions: RL = 10k, CL = 100pF. VDD = 5V 10%, VREF = 2.048V and VDD = 3V 10%, VREF = 1.024V over recommended operating freeair temperature range (unless noted otherwise). PARAMETER Digital Inputs High level input current Low level input current Input capacitance IIH IIL CI Input voltage = VDD Input voltage = 0V 8 1 1 A A pF SYMBOL TEST CONDITIONS MIN TYP MAX UNIT
Notes: 1. Integral non-linearity (INL) is the maximum deviation of the output from the line between zero and full scale (excluding the effects of zero code and full scale errors). 2. Differential non-linearity (DNL) is the difference between the measured and ideal 1LSB amplitude change of any adjacent two codes. A guarantee of monotonicity means the output voltage always changes in the same direction (or remains constant) as the digital input code. 3. Zero code error is the voltage output when the DAC input code is zero. 4. Gain error is the deviation from the ideal full-scale output excluding the effects of zero code error. 5. Power supply rejection ratio is measured by varying VDD from 4.5V to 5.5V and measuring the proportion of this signal imposed on the zero code error and the gain error. 6. Zero code error and Gain error temperature coefficients are normalised to full-scale voltage. 7. Output load regulation is the difference between the output voltage at full scale with a 10k load and 2k load. It is expressed as a percentage of the full scale output voltage with a 10k load. 8. Slew rate results are for the lower value of the rising and falling edge slew rates 9. Settling time is the time taken for the signal to settle to within 0.5LSB of the final measured value for both rising and falling edges. Limits are ensured by design and characterisation, but are not production tested. 10. SNR, SNRD, THD and SPFDR are measured on a synthesised sine wave at frequency fOUT generated with a sampling frequency fs.
WOLFSON MICROELECTRONICS LTD
PD Rev 1.0 November 2000
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Production Data
WM2624
SERIAL INTERFACE
tWL SCLK 1 tSUD DIN tSUCSFS NCS tWHFS FS tSUFS tSUC16FS D15 tHD D14 D13 D12 D1 D0 tSUC16CS 2 tWH 3 4 5 15 16
Figure 1 Timing Diagram Test Conditions: RL = 10k, CL = 100pF. VDD = 5V 10%, VREF = 2.048V and VDD = 3V 10%, VREF = 1.024V over recommended operating free-air temperature range (unless noted otherwise). SYMBOL tSUCSFS tSUFS tSUC16FS TEST CONDITIONS Setup time CSB low before falling FS edge. Setup time FS low before first falling SCLK edge. Setup time, 16 falling SCLK edge after FS low on which data bit D0 is sampled before rising edge of FS. Setup time, 16 rising SCLK edge (first after data bit D0 sampled) before CSB rising edge. If FS is used instead of the 16th rising edge to update the DAC, this setup time is between the FS rising edge and the CSB rising edge. Pulse duration, SCLK high. Pulse duration, SCLK low. Setup time, data ready before SCLK falling edge. Hold time, data held valid after SCLK falling edge. Pulse duration, FS high.
th th
MIN 10 8 10
TYP
MAX
UNIT ns ns ns
tSUC16CS
10
ns
tWH tWL tSUD tHD tWHFS
25 25 8 5 25
ns ns ns ns ns
WOLFSON MICROELECTRONICS LTD
PD Rev 1.0 November 2000
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WM2624 TYPICAL PERFORMANCE GRAPHS
0.2 VDD = 2.7V, VREF = 1.024V, Speed = Fast Mode 0.15
Production Data
0.1 INL - Integral Non-Linearity (LSBs)
0.05
0
-0.05
-0.1
-0.15
-0.2 0 32 64 96 128 DIGITAL CODE 160 192 224 256
Figure 2 Integral Non-Linearity
0.4 0.4
VDD = 3V, VREF = 1V, Input Code = 0
0.35 0.35
VDD = 5V, VREF = 2V, Input Code = 0
0.3
0.3
0.25
OUTPUT VOLTAGE - V
OUTPUT VOLTAGE - V
0.25
0.2
0.2
0.15
0.15
0.1
0.1
0.05
0.05
0 0 1 2 3 4 5 ISINK - mA 6 7 8 9
Slow
0 10
Fast
0
1
2
3
4
5 ISINK - mA
6
7
8
Slow
9
10
Fast
Figure 3 Sink Current VDD = 3V
2.06
Figure 4 Sink Current VDD = 5V
4.1
VDD = 3V, VREF = 1V, Input Code = 4095
2.055 4.095
VDD = 5V, VREF = 2V, Input Code = 4095
2.05 OUTPUT VOLTAGE - V OUTPUT VOLTAGE - V 0 1 2 3 4 5 ISOURCE - mA 6 7 8 9
Slow
4.09
2.045
4.085
2.04
4.08
2.035
4.075
2.03
4.07
2.025 10
Fast
4.065 0 1 2 3 4 5 ISOURCE - mA 6 7 8 9
Slow
10
Fast
Figure 5 Source Current VDD = 3V
Figure 6 Source Current VDD = 5V
WOLFSON MICROELECTRONICS LTD
PD Rev 1.0 November 2000
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Production Data
WM2624
DEVICE DESCRIPTION
GENERAL FUNCTION
The WM2624 is an 8-bit, voltage output DAC operating from a single supply. It uses a resistor string network buffered with an op amp to convert 8-bit digital data to analogue voltage levels (see Block Diagram). The output voltage is determined by the reference voltage and the input code according to the following relationship:
V = 2 VREF out
( ) CODE
256
INPUT 1111 : 1000 0001 1111
OUTPUT
2 VREF
( ) 255
256
:
2 VREF
( ) 129
256
256
REF
1000
0000
2 VREF
( ) 128 = V
2 VREF
0111 : 0000 0000
1111
( ) 127
:
256 1 256
0001 0000
2 VREF
()
0V
Table 1 Binary Code Table (0V to 2VREF Output), Gain = 2
POWER ON RESET
An internal power-on-reset circuit resets the DAC register to all 0s on power-up.
BUFFER AMPLIFIER
The output buffer has a near rail-to-rail output with short circuit protection and can reliably drive a 2k load with a 100pF load capacitance.
SERIAL INTERFACE
Before writing any data to the WM2623, the device must first be enabled by setting CSB to low. Then, a falling edge of FS starts shifting the data bit-per-bit (starting with the MSB) into the internal register on the falling edges of SCLK. After 16 bits have been transferred, the next rising edge on SCLK or FS causes the content of the shift register to be moved to the DAC latch which updates the voltage output to the new level. The serial interface of the device can be used in two basic modes: * * four wire (with chip select) three wire (without chip select)
Using the chip select pin, CSB (four wire mode), it is possible to have more than one device connected to the serial port of the data source (DSP or microcontroller). If there is no need to have more than one device on the serial bus, CSB can be tied low.
WOLFSON MICROELECTRONICS LTD
PD Rev 1.0 November 2000
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WM2624
SERIAL CLOCK AND UPDATE RATE
Figure 1 shows the device timing. The maximum serial rate is:
Production Data
f SCLK max =
1 = 20 MHz tWH min + tWL min
Since a data word contains 16 bits, the sample rate is limited to
f s max =
1 = 1.25MHz 16(tWH min + tWL min )
However, the DAC settling time to 8-bit accuracy limits the response time of the analogue output for large input step transitions.
SOFTWARE CONFIGURATION OPTIONS
Table 2 shows the composition of a 16-bit data word. When writing to the DAC, R1, R0 and D3 through D0 should be set to ZERO. D11-D4 contains the 8-bit DAC data, and D14-D13 hold the programmable options. D15 D14 D13 D12 D11 D10 D9 D8 D7 D6 R1 SPD PWR R0 New DAC value (8 bits) Table 2 Register Map D5 D4 D3 0 D2 0 D1 0 D0 0
PROGRAMMABLE SETTLING TIME
SPD (Bit 14) allows for software control of the converter speed. A ONE selects the fast mode, where typical settling time to within 0.5LSB of the final value is 1s. a ZERO puts the device into the slow mode, where typical settling time is 3.5s.
PROGRAMMABLE POWER DOWN
The power down function is controlled by PWR (Bit 13). A ZERO configures the device as active, or fully powered up, a ONE configures the device into power down mode. When the power down function is released the device reverts to the DAC code set prior to power down.
ADDRESSING THE CONTROL REGISTER
A separate internal control register is available. When R1 and R0 (data bits D15 and D12) are set to ONE, incoming data is written to the control register instead of the DAC latch. R1 (BIT D15) 0 0 1 1 R0 (BIT D12) 0 1 0 1 Reserved Reserved Write data to control register REGISTER Write data to DAC
Table 3 Register Access Control The contents of the control register, shown below in Table 4, are used to program the internal reference function. D11 x D10 x D9 X D8 x D7 x D6 x D5 x D4 x D3 x D2 X D1 D0 REF1 REF0
Table 4 Control Register Contents
WOLFSON MICROELECTRONICS LTD
PD Rev 1.0 November 2000
8
Production Data
WM2624
PROGRAMMABLE INTERNAL OR EXTERNAL REFERENCE
The reference can be sourced internally or externally under software control. If an external reference voltage is applied to the REF pin, the device must be configured to accept it. This will activate the reference input buffer, whose input resistance of 10M (typical) makes the reference input resistance independent of code. When using the on-chip reference, voltages of 1.024V or 2.048V are available. The internal reference can source up to 1mA on the REF pin and can therefore be used as a system reference for external components. REF1 0 0 1 1 REF0) 0 1 0 1 REGISTER Use external reference Use internal 1.024V reference Use internal 2.048V reference Use external reference
Table 5 Programmable Internal Reference Examples: 1. Use internal 2.048V reference voltage D9 x D8 x D7 x D6 x D5 x D4 x D3 x D2 x D1 1 D0 0
D15 D14 D13 D12 D11 D10 1 x 0 1 x x
2.
Write new DAC value and update DAC output D9 D8 D7 D6 New DAC value D5 D4 D3 0 D2 0 D1 0 D0 0
D15 D14 D13 D12 D11 D10 0 x 0 0
WOLFSON MICROELECTRONICS LTD
PD Rev 1.0 November 2000
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WM2624 APPLICATIONS INFORMATION
LINEARITY, OFFSET, AND GAIN ERROR
Production Data
Amplifiers operating from a single supply can have positive or negative voltage offsets. With a positive offset, the output voltage changes on the first code transition. However, if the offset is negative, the output voltage may not change with the first code, depending on the magnitude of the offset voltage. This is because with the most negative supply rail being ground, any attempt to drive the output amplifier below ground will clamp the output at 0 V. The output voltage then remains at zero until the input code is sufficiently high to overcome the negative offset voltage, resulting in the transfer function shown in Figure 7.
Output Voltage 0V Negative Offset DAC code
Figure 7 Effect of Negative Offset This offset error, not the linearity error, produces the breakpoint. The transfer function would follow the dotted line if the output buffer could drive below the ground rail. DAC linearity is measured between zero-input code (all input bits at 0) and full-scale code (all inputs at 1), disregarding offset and full scale errors. However, due to the breakpoint in the transfer function, single supply operation does not allow for adjustment when the offset is negative. In such cases, the linearity is therefore measured between full-scale and the lowest code that produces a positive (non-zero) output voltage.
POWER SUPPLY DECOUPLING AND GROUNDING
Printed circuit boards with separate analogue and digital ground planes deliver the best system performance. The two ground planes should be connected together at the low impedance power supply source. Ground currents should be managed so as to minimise voltage drops across the ground planes. A 0.1F decoupling capacitor should be connected between the positive supply and ground pins of the DAC, with short leads as close as possible to the device. Use of ferrite beads may further isolate the system analogue supply from the digital supply.
WOLFSON MICROELECTRONICS LTD
PD Rev 1.0 November 2000
10
Production Data
WM2624
PACKAGE DIMENSIONS
D: 8 PIN SOIC 3.9mm Wide Body DM009.B
e
B
8
5
E
H
1
4
L
D h x 45o
A
A1 -C-
C
0.10 (0.004)
SEATING PLANE
Symbols A A1 B C D e E h H L REF:
Dimensions (mm) MIN MAX 1.35 1.75 0.10 0.25 0.33 0.51 0.19 0.25 4.80 5.00 1.27 BSC 3.80 4.00 0.25 0.50 5.80 6.20 0.40 1.27 o o 8 0
Dimensions (Inches) MIN MAX 0.0532 0.0688 0.0040 0.0098 0.0130 0.0200 0.0075 0.0098 0.1890 0.1968 0.050 BSC 0.1497 0.1574 0.0099 0.0196 0.2284 0.2440 0.0160 0.0500 o o 0 8
JEDEC.95, MS-012
NOTES: A. ALL LINEAR DIMENSIONS ARE IN MILLIMETERS (INCHES). B. THIS DRAWING IS SUBJECT TO CHANGE WITHOUT NOTICE. C. BODY DIMENSIONS DO NOT INCLUDE MOLD FLASH OR PROTRUSION, NOT TO EXCEED 0.25MM (0.010IN). D. MEETS JEDEC.95 MS-012, VARIATION = AA. REFER TO THIS SPECIFICATION FOR FURTHER DETAILS.
WOLFSON MICROELECTRONICS LTD
PD Rev 1.0 November 2000
11

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